PIC16LF84A-04I/SS【PDF 43/80 页】IC MCU FLASH 1KX14 EE 20SSOP

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Sheet目录3833

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Micrel, Inc.

KSZ8851SNL/SNLI

August 2009

M9999-083109-2.0

Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3

This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte

of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.

Bit

Default Value

R/W

Description

15-0

WF3BM3

Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a

Wake up frame 3 pattern.

0x6C – 0x6F: Reserved

Transmit Control Register (0x70 – 0x71): TXCR

This register holds control information programmed by the CPU to control the QMU transmit module function.

Bit

Default Value

R/W

Description

15-9

Reserved

0x0

TCGICMP Transmit Checksum Generation for ICMP

When this bit is set, The KSZ8851SNL is enabled to transmit ICMP frame (only for non-

fragment frame) checksum generation.

0x0

Reserved

0x0

TCGTCP Transmit Checksum Generation for TCP

When this bit is set, The KSZ8851SNL is enabled to transmit TCP frame checksum

generation.

0x0

TCGIP Transmit Checksum Generation for IP

When this bit is set, The KSZ8851SNL is enabled to transmit IP header checksum

generation.

0x0

FTXQ Flush Transmit Queue

When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.

Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to

normal operation.

0x0

TXFCE Transmit Flow Control Enable

When this bit is set and the KSZ8851SNL is in full-duplex mode, flow control is enabled.

The KSZ8851SNL transmits a PAUSE frame when the Receive Buffer capacity reaches a

threshold level that will cause the buffer to overflow.

When this bit is set and the KSZ8851SNL is in half-duplex mode, back-pressure flow

control is enabled. When this bit is cleared, no transmit flow control is enabled.

0x0

TXPE Transmit Padding Enable

When this bit is set, the KSZ8851SNL automatically adds a padding field to a packet

shorter than 64 bytes.

Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors

for the transmit packet.

0x0

TXCE Transmit CRC Enable

When this bit is set, the KSZ8851SNL automatically adds a 32-bit CRC checksum field to

the end of a transmit frame.

0x0

TXE Transmit Enable

When this bit is set, the transmit module is enabled and placed in a running state. When

reset, the transmit process is placed in the stopped state after the transmission of the

current frame is completed.

Transmit Status Register (0x72 – 0x73): TXSR

This register keeps the status of the last transmitted frame.

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